一段状态机示例

`timescale 1ns / 1ps
module mystate(input clk,input rst,output [2:0] out);
reg[2:0] state;
always@(posedge clk)
begin
    if(!rst)
        state <= 2'b00;
    else if(state == 2'b00)
        state <= 2'b01;
     else if(state == 2'b01)
        state <= 2'b10;
     else if(state == 2'b10)
        state <= 2'b11;
     else 
        state <= 2'b00;
end
assign out = state;
endmodule

测试示例：

`timescale 1ns / 1ps
module Hellotmystate();
    wire[2:0] myout;
    reg rst;
    reg clk;
    mystate myinstance(
    .clk(clk),
    .rst(rst),
    .out(myout)
    );
    initial begin
        rst = 0;
        clk = 0;
        #10
        rst = 1;
    end
    always #5 clk =~clk;
endmodule

仿真结果：

输出为reg类型:

module mystate(input clk,input rst,output reg[10:0] count );
always@(posedge clk)
begin
    if(!rst)
        count<=10'b0;
     else
        count<= count+3;
end
endmodule